Google LLC is reportedly preparing to collaborate with Taiwanese semiconductor company MediaTek on the next version of its Tensor Processing Units (TPUs), the company’s proprietary AI chips.
According to The Information, which relies on an internal source, MediaTek could begin manufacturing the next generation of TPUs as early as next year. Google currently partners with Broadcom for the production of its TPU chips. Although MediaTek may take over production of the next generation chips, Google has not terminated its relationship with Broadcom for the time being.
Large-scale computing
Google’s TPUs are custom-designed Application-Specific Integrated Circuits (ASICs). They accelerate machine learning workloads, particularly those involving neural networks. The chips are specifically optimized for Google’s TensorFlow framework. They enhance both the training and inference of AI models by efficiently handling the computational demands of deep neural networks.
TPUs differ from conventional processors in their design for large-scale, low-precision computation. This specialization enables TPUs to deliver substantial performance improvements and energy efficiency compared to general-purpose CPUs and GPUs.
For cloud applications, TPUs are incorporated into Google’s data centers to deliver scalable and efficient computing resources for extensive machine learning tasks. For edge computing applications, Google offers the Edge TPU, a compact and energy-efficient variant that brings AI capabilities to devices like smartphones and IoT applications.
Less reliance on Nvidia
As Reuters points out, the capability to produce in-house AI chips provides Google with a strategic advantage in the AI competition. This is because it reduces Google’s dependence on Nvidia, which currently dominates the AI chip market.
The most recent iteration of Google TPUs was the sixth generation, known as the Trillium TPU, announced in October. Trillium delivers a fourfold improvement in AI training performance, along with a threefold enhancement in inference throughput compared to its predecessor.
Additionally, Trillium TPUs feature increased memory and bandwidth, allowing them to process larger language models with more parameters and expanded key-value caches. The chip supports a broader range of model architectures for both training and inference operations.